1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a method of fabricating a substrate-based semiconductor package without mold flash.
2. Description of Related Art
A substrate-based semiconductor package is a type of semiconductor package that utilizes a circuited substrate as chip carrier for mounting one or more semiconductor chips thereon. BGA (Ball Grid Array) package is an example of substrate-based semiconductor package. Typically, a semiconductor package substrate is formed with a predefined pattern of electrically-conductive traces serving as signal lines for electrically connecting the packaged semiconductor chip to external connecting points.
FIGS. 1A-1D are schematic diagrams showing a conventional method for fabricating a substrate-based semiconductor package (note that these drawings are simplified schematic diagrams showing only a small number of components that are related to the invention for demonstrative purpose, and which are not drawn to actual sizes and scales in practical applications; the practical layout on the semiconductor package may be much more complex).
Referring to FIG. 1A and FIG. 1B, this semiconductor package is constructed on a substrate 100 as chip carrier. The substrate 100 is partitioned by a predefined mold border line MBL into a molding region 101 and a non-molding region 102; wherein the molding region 101 is the region where an encapsulation body (shown later in FIG. 1D with the reference numeral 160) is to be molded, while the non-molding region 102 is the region beyond the molding region 101 that is not to be encapsulated.
Further, the substrate 100 is formed with a predefined pattern of electrically conductive traces 110 on the front side thereof, each trace 110 having an inner terminal 111 located within the molding region 101 and an outer terminal 112 located outside the molding region 101. Next, a solder mask 120 is formed from an electrically-insulative material over the substrate 100 to cover the traces 110 while exposing necessary bonding points.
In the die-bonding process, at least one semiconductor chip 130 is mounted over the molding region 101 of the substrate 100, and which is then electrically connected to the inner terminals 111 of the traces 110 by means of bonding wires 140.
Referring further to FIG. 1C, in the next step, a molding process is performed by using a molding tool 150 having a hollowed cavity 151; wherein the semi-finished package assembly shown in FIG. 1A is fixed in the cavity 151 of the molding tool 150, with the inner wall 152 of the cavity 151 being aligned to the predefined mold border line MBL on the substrate 100. A molding material 153, such as epoxy resin, is then injected through an injection path (not shown) into the cavity 151 of the molding tool 150 until filling up the entire void space of the cavity 151.
Referring further to FIG. 1D, as the foregoing molding process is completed, an encapsulation body 160 is formed over the molding region 101 of the substrate 100 to encapsulate the semiconductor chip 130.
One problem to the foregoing packaging process, however, as shown in FIG. 2A, in the case of some of the traces 110 are spaced at overly large intervals across the mold border line MBL (as for example the two traces 110a, 110b shown in FIG. 1B), it would undesirably cause mold flash 170 over the non-molding region 102 of the substrate 100 just outside the encapsulation body 160. This is because that, in the case of FIG. 1B, the traces 110 are designed in such a manner that the interval D1 between the two neighboring traces 110a, 110b is overly larger than the normal interval D2 between the next neighboring pair of traces 110b, 110c; and as illustrated in FIG. 2B, when the solder mask 120 is coated over the substrate 100, this overly-large interval D2 would cause a recessed portion 121 in the part of the solder mask 120 that is located between these two neighboring traces 110a, 110b. As further illustrated in FIG. 2C, during the molding process, this recessed portion 121 would result in a leakage hole for the molding material 153 injected into the cavity 151 of the molding tool 150 (see FIG. 1C), thus undesirably causing the mold flash 170. The presence of this mold flash 170 over the substrate 100 would undesirably degrade the quality of the finished semiconductor package.
Related patents, include, for example, the U.S. Pat. No. 5,744,084 entitled xe2x80x9cMETHOD OF IMPROVING MOLDING OF AN OVERMOLDED PACKAGE BODY ON A SUBSTRATExe2x80x9d. This patented technology is characterized by the use of a dam structure to prevent mold flash. One drawback to this solution, however, is that the provision of the dam structure is quite complex in process and thus would considerably increase the overall fabrication cost.
It is therefore an objective of this invention to provide a new method of fabricating a substrate-based semiconductor package, which can help prevent the above-mentioned problem of mold flash while is more cost-effective to implement.
The method according to the invention comprising the step of: (1) preparing a substrate having one surface partitioned by a predefined mold border line into a molding region and a non-molding region: (2) providing a plurality of electrically-conductive traces over the substrate, each trace having an inner terminal located within the molding region and an outer terminal located within the non-molding region; (3) providing a plurality of dummy traces across the mold border line and interposed between those electrically-conductive traces that are spaced at an interval greater than a predetermined distance that is destined to cause mold flash; (4) providing a solder mask over the substrate to cover the electrically-conductive traces and the dummy traces; and (5) performing a molding process to form an encapsulation body on the molding region of the substrate.
The method of the invention is characterized by the provision of one or more dummy traces between each overly-spaced pair of signal traces to help the solder mask covering over these traces to be substantially planarized in its top surface without the undesired forming of a recessed portion that would otherwise cause leakage of molding material to the outside to the molding region during molding process. Owing to the provision of these dummy traces, no leakage hole would exist between the molding tool and the solder mask, thus preventing mold flash. The proposed method therefore allows the finished semiconductor package to be more assured in quality.